Monolithic microwave wide-band VCO

ABSTRACT

A monolithic microwave voltage-controlled oscillator including one or more FETS integrated with a wide-ratio varactor. The varactor includes interdigitated anode and cathode patterns laid out on a single thin epitaxial layer. The punch through voltage of the epitaxial layer, and hence the resistivity-thickness product of the epitaxial layer, must be low. Since the substrate is semi-insulating, punch through to the substrate does not become uncontrollable, but simply permits modulation of the capacitance over a very wide range. The FETS are formed in the same epitaxial layer with the varactor, and complicated doping profiles are not required.

CROSS-REFERENCE TO RELATED APPLICATIONS

The following applications of common assignee and filed concurrentlywith the present application contain related subject matter and arehereby incorporated by reference: .[.TI-8887.]..Iadd.Ser. No. 292,770now abandoned.Iaddend., Wide-Ratio Monolithic Microwave Varactor;.[.TI-8990.]..Iadd.Ser. No. 292,862, now U.S. Pat. No.4,719,434.Iaddend., Varactor Trimming for MMICs; .[.TI-900.]..Iadd.Ser.No. 292,769, now U.S. Pat. No. 4,463,372.Iaddend., Self-Biasing forFET-Driven Microwave VCOs.

BACKGROUND OF THE INVENTION

The present invention integrates a varactor diode which has a very largetuning ratio (i.e. a wide-ratio diode) in a monolithic microwaveintegrated circuit (MMIC), to provide a wide-band microwavevoltagecontrolled oscillator (VCO).

Conventional varactor diodes, particularly those with large tuningratios (hyperabrupt diodes) require highly conductive substrate materialand relatively thick epitaxial layers (greater than one micron). Thesematerial requirements are not compatible with the requirements of GaAsFET-monolithic microwave integrated circuits (MMICS) which require athin (less than one-half micron) uniformly doped active layer on asemi-insulating substrate. To integrate the conventional hyperabruptdiode on a semi-insulating substrate requires a very complicatedselective epitaxial deposition, wherein certain areas of the substratesurface receive one epitaxial layer, and other areas receive a differentepitaxial layer. The materials required to implement a varactor in anMMIC should be the same as or similar to those for an FET, so thatvaractors can easily be integrated in, e.g., monolithic microwavevoltage controlled oscillators.

Thus, it is an object of the present invention to provide a monolithicmicrowave integrated circuit incorporating a wide-ratio varactor in athin uniformally doped active layer above a semi-insulating substrate.

R. VanTuyl, "A Monolithic GaAs FET RF Signal Generation Chip", ISSCC-80Digest 118 (which is hereby incorporated by reference) discloses agallium arsenide varactor diode in an MMIC which is integrated in a thinepitaxial layer on a semi-insulating substrate. The VanTuyl device doesnot, however, provide very wide capacitance tuning characteristics. Awide capacitance range (of a decade or more) is essential for manymicrowave applications. In addition, the VanTuyl device is designed foroperation only at lower microwave frequencies (of at most 4 GHz).

The frequency tuning range of a varactor-based VCO is much narrower thanthe capacitance range of the tuning varactor, due to the inherent andparasitic reactance characteristics of FETs and other components of theVCO. In particular, an extremely wide-range varactor (having acapacitance ratio of a decade or more) is needed if the frequency rangeof the VCO is to remotely approach one octave.

Thus, it is an object of the present invention to provide a VCO having atuning range of 1.5 to 1 or larger at microwave frequencies. It is afurther object of the present invention to provide a VCO having a tuningrange of 1.3 to 1 or better at microwave frequencies above 5 GHz.

It is a further object of the present invention to provide a microwaveVCO having a tuning range of an octave or more.

It is a further object of the present invention to provide a monolithicmicrowave VCO having a tuning range of 1.5 to 1 or larger.

A major difficulty which arises in microwave VCOs having such a largefrequency range is maintaining the correct impedance match to achievethe maximum obtainable bandwidth. Mismatch can easily become such as togravely impair performance.

However, in a monolithic microwave integrated circuits even trimming (toachieve impedance match at one particular frequency) is difficult, andoptimal matching over a wide range of frequencies is presentlyimpossible.

Thus, it is a further object of the present invention to provide meansfor maintaining impedance matching of a monolithic microwave wide-bandVCO over a very large frequency range.

At the present, YIG devices provide the only practical means of widetuning at higher microwave frequencies, e.g., 10 GHz. However, not onlya such YIG structures require very complex magnetic-field-controlledtuning structures, but also the capacitance (or frequency) changepermitted by YIG devices is very slow, on the order of a millisecond ormore.

Thus, it is a further object of the present invention to provide amicrowave reactance which can be tuned over an extremely wide range withgreat rapidity. In particular, it is an object of the present inventionto provide a microwave reactance which can be tuned over a wide rangewith great rapidity at frequencies in excess of 5 GHz.

Some examples of prior art integrated varactors include: U.S. Pat. Nos.3,396,312 to Vendelin, 3,559,005 to Vandelin et al, and 3,636,420 toVandelin et al.

SUMMARY OF THE INVENTION

The wide-range integrated varactor used in the VCO of the presentinvention includes an interdigitated anode and cathode on a thinepitaxial or implanted layer on a semi-insulating substrate. Theepitaxial layer must have a small doping-thickness product, so thatpunchthrough occurs before breakdown. Preferably the anode forms aSchottky barrier with the epitaxial layer. Preferably, the substrate isCr-doped GaAs, and the epitaxial layer is n-type GaAs. As punch-throughoccurs the effective area of the anode (and hence the capacitance)changes from a large depletion boundary below the surface anode to anapproximately vertical section through the epitaxial layer. Since thesubstrate is semi-insulating, punch-through does not becomecatastrophic.

In the preferred embodiment, two such monolithic varactors areintegrated with one FET. One of the varactors is used to provide thenecessary variable capacitance for the VCO, and the other varactor isused to maintain impedance matching in the source circuit of the VCO. Inaddition, conventional reactive elements are also used to providematching.

According to the present invention, there is provided: a monolithicmicrowave voltage-controlled oscillator (VCO), comprising: asemi-insulating substrate; a doped semiconducting layer above saidsubstrate; an FET atop said semiconductor layer, said FET comprising amutually interdigitated source and drain, and a gate interposed betweensaid source and said drain; an input contact connected to a first one ofsaid source and said drain, and an output contact connected to the otherone of said source and said drain; a varactor, comprising an anode and acathode atop said semiconducting layer, said anode forming a Schottkybarrier with said semiconducting layer, the portion of saidsemiconducting layer beneath said anode being sufficiently thin andsufficiently lightly doped that punch through between said anode andsaid substrate occurs at a lower voltage than does breakdown betweensaid anode and said cathode; and means for providing a bias voltage,connected to a first one of said anode and said cathode of saidvaractor, said gate of said FET being connected to the other one of saidanode and said cathode of said varactor.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be described with reference to theaccompanying drawings, wherein:

FIG. 1 is a top view of the varactor diode used in the presentinvention;

FIG. 2 is a cross-sectional elevation of one finger of the varactordiode used in the present invention;

FIG. 3 shows a sample capacitance/voltage curve of the varactor formedaccording to the present invention;

FIG. 4 compares the capacitance/voltage characteristics of asingle-finger and of a six-finger varactor suitable for use in thepresent invention; and,

FIG. 5 shows first and second embodiments of a VCO according to thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a top plan view of the varactor used in the present invention.Ion implantation (e.g., 5×10¹² /cm² of Si at 200 keV) forms an n-typelayer 10 on a semi-insulating substrate (preferably Cr-doped GaAs).Alternatively epitaxial growth may be used to form the layer 10. Ananode 14 and a cathode 16 are then formed in an interdigitated relationabove the n-type layer 10. The anode forms a Schottky barrier withrespect to the n-type layer 10, and the cathode 16 forms an ohmiccontact.

Each finger of the anode is preferably 6 microns wide and 150 micronslong. The anode is a deposited layer of, for example, Ti/Pt/Au. Thespacing between the anode and cathode is nominally 2 microns.

FIG. 2 shows a cross section across one finger of the anode 14 andportions of two fingers of the cathode 16. The dotted lines V₀ and V_(b)show the respective depletion regions adjacent the anode at 0 volts andat the breakdown voltage, respectively. As these curves show, theeffective area of the anode between the punch through voltage and thebreakdown voltage is limited to only the approximately vertical portion18 of the depletion boundary V_(b). By contrast, at 0 bias the anode 14has the effective area shown by the depletion boundary V₀, which isslightly larger than the physical area of the anode 14 itself.

Thus, a wide capacitance ratio is achieved, because the doping/thicknessproduct of the epitaxial layer 10 is controlled to allow punch throughbefore breakdown. In the preferred embodiment, the layer 10 is 300nanometers thick. If the thickness is greater than 300 nm, theconcentration of impurities should be reduced proportionately. At punchthrough, the effective diode area is reduced to that of the sidewall. Asa result, a very large capacitance ratio is achieved by proper choice ofthe geometry.

In practice, a tradeoff must be made between the Q and the capacitanceratio. The Q is limited by the parasitic series resistance for currentflowing laterally under the anode before punch-through. Since thecurrent beneath the anode is confined to the region of epitaxial layer10 which lies beneath the depletion boundary and this layer becomesthinner as the depletion boundary approaches punch-through, a largeeffective series resistance appears just before punch-through.

After punch-through, this series resistance is reduced to that of onlythe region from the vertical depletion boundary 18 to the cathode 16,and very high Q's are observed. This series resistance is, of course,larger if the finger width is larger.

To reduce the punch-through voltage, a recess may be etched out underthe whole surface of the anode, before the anode metallization isdeposited. Thus, for example, where the layer 10 is 300 nanometersthick, 100 nanometers would be etched away before the anode isdeposited. Thus, the punch-through voltage is reduced, since the anodeis accordingly closer to the substrate, whereas the breakdown voltage isnot reduced, since the anode is no closer to the cathode. In fact, thebreakdown voltage may be slightly increased, since the surface portionsof the layer 10 are likely to be slightly more heavily doped than thelower portions of the layer 10. Since such recessed structures arefrequently used for the channel regions of microwave FETs, to reduce theseries resistance of the source and drain regions adjacent the channel,such an anode recess is also compatible with familiar microwaveintegrated circuit technology. An anode which is recessed in thisfashion, to approximately 1/3 of the depth of the layer 10, constitutesthe presently preferred embodiment of the varactor.

FIG. 3 shows the capacitance/voltage characteristics of a varactorconstructed for use in the present invention. A 6 by 150 micron Ti/Pt/Auanode finger is placed between cathode areas two microns away. The layer10 is 300 nm thick n-type ion implanted gallium arsenide, like that usedfor FETs. The substrate is chromium doped gallium arsenide. The anode isplaced in a 100 nm etched recess, so that the anode is 200 nm above thesubstrate. In this embodiment, the capacitance decreases from 1.96 pF at0 bias to 0.04 pF at -7 volts. This 49 to 1 capacitance ratio isachieved because of the extremely rapid capacitance decrease as punchthrough occurs between 5 and 7 volts. Calculated cutoff frequency forthis diode is 28 GHz at 0 volts bias and 2.5 THz at 10 volts.

Of course, multi-finger embodiments of this planar varactor design mayalso be constructed.

The implantation parameters which optimize the n-type region 10 forconstruction of the varactor according to the present invention may beslightly different from those used to optimize the epitaxial layer forconstruction of FETs. For example, a slightly lower implantation dose(e.g. 3×10¹² /cm²) at a slightly higher energy (e.g. 400 KeV) would beused to construct a varactor according to the present invention, toobtain higher breakdown voltage. Thus, selective implantation of amonolithic chip containing both varactors and FETS would permitoptimization of performance. However, the required characteristics forFETs and for the varactor according to the present invention aresufficiently close that, although selective implantation can provide amarginal advantage and performance, it is not required.

Passivation, in the presently preferred embodiment, is achieved by thefollowing sequence of processing steps: First, the cathode metallizationis deposited. Then 1000 Angstroms of silicon nitride are deposited overthe whole surface of the device. The anode recess is then patterned andetched, to approximately 1/3 of the thickness of the layer 10. The anodemetallization is then deposited, and any necessary contacts are thenformed. Finally, 3000 Angstroms more of silicon nitride are depositedoverall. Clean-up, at approximately intermediate points of the process,is performed using, e.g., ammonium hydroxide and water.

To further improve varactor performance, by further increasing thebreakdown voltage, additional steps may alternatively be inserted toreduce the density of surface states. For example, an additional etchingstep may be applied overall, after the anode has been deposited, or anadditional reagent may be used for clean-up.

Nitride assisted lift-off, if used to form the anode 14, improves thebreakdown voltage of the varactors of the present invention. Thistechnique places the anode metal back from the edge of the etchedrecess, and passivates the surface of the gallium arsenide. Theparameters for this process are well known to those skilled in the art,(see, e.g. Proceedings of the Cornell Conference on MicrowaveSemiconductor Devices, 1981, p. 157, "High Yield, Reproducible processTechniques for microwave GaAs FETs", G. E. Brehm, F. H. Doerbeck, W. R.Frensley, H. M. Macksey, and R. E. Williams).

As will be obvious to those skilled in the art, numerous modificationsmaybe performed, within the scope of the inventive concepts describedabove, to construct a varactor for use in the present invention. Forexample, p-type material could be used in the layer 10, althoughdifferent metal composition would be required to create a Schottkybarrier contact. Other semiconductor materials could also be used,provided that a doped semiconducting layer was lattice-matched to asemi-insulating substrate.

Two embodiments of integrated microwave wideband VCOs according to thepresent invention are shown in FIG. 5. The VCO circuit 22, shown on theleft, represents the presently preferred embodiment. The VCO 22 is a"common gate" oscillator, having loop inductors 54 and 56 and varactors50 and 52 respectively connected from the gate and source terminals ofFET 58 to RF ground. MIM capacitors 78 and 80 (each numeral 16 pF) toground are used for RF bypassing, and 2.5 kilohm GaAs resistors areincluded at 74 and 76 are included in the high impedance bias lines tohelp suppress low frequency oscillations, to aid in isolating the DCbias lines from RF, and to act as a DC current limit. Bonding pads 72and 70 are respectively provided for the gate and source tuning varactorvoltages and pad 66 for DC-grounding of the source 64. External means ofbiasing the drain 62 and of matching the drain output 68 to 50 ohms mustbe provided.

No DC return is provided for the gate, since the bias point for the gateis established by clipping the RF gate voltage. This occurs in the FET58, as described below.

While the structure of the FET is in almost all respects conventional,it does have one important feature which cooperates in the noveloperation of the VCO according to the present invention. The gatefingers form a Schottky barrier with the channel region, and thus RFvoltages in the gate circuit are clipped by the Schottky barrier to formthe necessary gate bias. This has the outstanding advantage that thegate tuning network in the present invention consists simply of theinductor 54 and the varactor 50, and other circuits normally required toestablish the gate operating point, which would have high frequencyresonances, are not included. This permits easy operation of a microwaveoscillator over an extremely broad bandwidth.

Thus, the processing steps required to form the monolithic VCO inaccordance with the present invention, as described above, are asfollows: the starting material is an n-type epitaxial (or implanted)layer on a semi-insulating substrate, preferably n-type GaAs on aCR-doped GaAs substrate. (1). A mesa etch step is first. Photoresist isapplied and patterned, and the epitaxial layer is then etchedaccordingly, to remove all portions of the epitaxial layer which are notneeded. For example, portions of the epitaxial layer are left where thevaractors 50 and 52 will be formed, and where the channel region of FET58 will be formed. Portions of the epitaxial layer are also used to formthe resistance elements 74 and 76. (2). Alignment marks are thendeposited and etched, to provide E-beam control. A silicon nitrideprotective layer, of e.g. 1000 Angstroms, is then deposited only overthe align marks. (Alignment marks are not shown within the VCO 22 ofFIG. 5, but the positioning and use of E-beam alignment marks within awafer is well known to those skilled in the art.) (3). Ohmic contactsare then formed. Photoresist is deposited and patterned to form thesource and drain regions of FET 58, and the respective cathodes ofvaractors 50 and 52. Au/Ge/Ni is then deposited, lift-off is performed,and alloying is then performed, all conventionally. (4). The next stageis gate patterning, 1000 Angstroms of silicon nitride is deposited overall. E-beam resist is deposited, and E-beam patterning is then appliedto define the gate fingers of FET 58 and the anode fingers of varactors50 and 52. The silicon nitride in these patterns is then etched, and theepitaxial layer is then etched, to approximately one third of itsthickness where it has been exposed. Thus, where the epitaxial layers3000 Angstroms thick, approximately 1000 Angstroms will be etched awayin the present step. Ti/Pt/Au is then deposited, to form Schottkybarriers to the epitaxial layer within these etched recesses, for thegate and anodes. Lift-off is then performed. (5). A first-levelmetallization step is then performed. 4000 Angstroms of silicon nitrideis deposited overall, and photoresist patterning and etching of thenitride is performed (conventionally) to define the first metallization.This includes the bottom plate 82 of the capacitors 78 and 80, theinductors 54 and 56, the contact pads 66, 68, 70, and 72, and most ofthe remaining wiring. The patterning at this stage also exposes thesource and drain fingers of the FET in the cathodes of the varactors 50and 52, so that more metal is deposited on these structures to lowertheir resistance. Life-off is then performed conventionally. (6). A topplate patterning step is then applied. First, 3000 Angstroms of siliconnitride are deposited overall. This nitride forms a passivating layerover the varactors 50 and 52, and also forms the dielectric layer of thetwo RF-grounding capacitors 78 and 80. The top plates of capacitors 78and 80 are then patterned (using photoresist), and TiAu is thendeposited. Lift-off is then conventionally performed. (7). Finally,air-bridge connections are formed. First, photoresist is patterned toform bias, where (e.g.) the air bridge 64 contacts the source contact66, the middle source finger 84, and the source finger 86. Nitrideetching is then performed where the bias have been patterned, and puregold is deposited by sputtering, The photoresist is not removed, but isleft in place, since it will be needed to support the air-bridge 64. Afurther layer of photoresist is then deposited, and patterned to formthe actual air bridge connection, and gold is then deposited byelectroplating. All photoresist is then stripped. As is well-known inthe art, such air-bridge structures have the advantage of reducing straycapacitance. For clarity, only one air-bridge connection is shown inFIG. 5, (across the source fingers of FET 58), but air-bridgeconnections are also generally used to connect first-and second-levelmetallizations. Thus, air-bridges are also preferably formed betweenvaractor 50 and the top plate of capacitor 78, and between varactor 52and capacitor 80.

Thus, the monolithic VCO 22 is connected to a power supply across sourceterminal 66 and drain terminal 68, and provides oscillator output powerat terminal 68. The source tuning terminal 70 and the gate tuningterminal 72 are used to provide bias voltages which respectively controlthe varactors 52 and 50. The varactor 50 is the primary tuning reactancefor the VCO, and the varactor 52 is used to tune the source circuit, toprovide optimal matching for broad-band capability.

The VCO 24 is generally similar, but the source-matching circuit is notincluded. The VCO 24 includes an FET 42, an inductance 40 and varactor26 in the gate line of FET 42, and an RF-grounding capacitor 38 and abias supply 32 and 34 connected to the cathode of the varactor 26. Sincethis VCO 24 does not have the source-matching circuit to providewide-band impedance matching, its potential bandwidth is only about 25%of that of the VCO 22. However, the VCO 24 does provide two advantagesover the VCO 22. First, the VCO 24 is physically smaller. Second, theVCO 24 is preferably operated in the common-drain mode, i.e. thepolarities of the off-chip source and drain connections are reversedfrom those used with VCO 22. Where the VCO 24 is constructed with300-micron total gate width, the source terminal provides an outputimpedance very close to 50 ohms, so that no separate impedance-matchingis required. Thus, where the broad-band capabilities of VCO 22 are notrequired, VCO 24 may be preferable. Like the VCO 22, the VCO 24 containsthe innovative provision discussed above for gate bias, without any DCreturn line.

What we claim is:
 1. A monolithic wideband microwave voltage-controlledoscillator (VCO), comprising:a semi-insulating substrate; a dopedsemiconducting layer above said substrate; an FET comprising a sourceand drain .Iadd.contacting a channel .Iaddend.in said semiconductinglayer, and a gate interposed between said source and said drain; .[.aninput.]. .Iadd.a first .Iaddend.contact connected to one of said sourceand said drain, and an output contact connected to the other of saidsource and said drain; a varactor, comprising a first terminal andsecond term terminal atop said semiconducting layer, said first terminalforming a barrier contact with said semiconducting layer, the portion ofsaid semiconducting layer beneath said first terminal being sufficientlythin and sufficiently lightly doped that punch through between saidfirst terminal and said substrate occurs at a lower voltage .[.then.]..Iadd.than .Iaddend.does breakdown between said first terminal and saidsecond terminal; and means for providing a bias voltage, connected to afirst one of said terminals of said varactor, said gate of said FETbeing direct current connected to the other .[.one.]. of said terminalsof said varactor.
 2. The VCO of claim 1, wherein said semi-insulatingsubstrate comprises a chromium-doped gallium arsenide.
 3. The VCO ofclaim 2, wherein said doped semiconducting layer comprises n-typegallium arsenide.
 4. The VCO of claim 3, wherein said dopedsemiconducting layer is less than one-half micron thick.
 5. The VCO ofclaim 1, wherein said output contact is connect to said source.
 6. TheVCO of claim 5, wherein said source and drain each comprise respectivepluralities of fingers, and said drain comprises a larger number of saidfingers than does said source.
 7. The VCO of claim 6, further comprisinga capacitor including a first and second metal plates and a dielectrictherebetween, said first plate of said capacitor being connected to saidother one of said anode and said cathode of said varactor, and saidsecond metal plate of said capacitor being connected to said drain ofsaid FET.
 8. The VCO of claim 7, further comprising an inductanceinterposed between said gate of said FET and said other one of saidanode and said cathode of said varactor.
 9. The VCO of claim 7, whereinsaid gate of said FET is connected to said anode of said varactor. 10.The VCO of claim 9, wherein the total length of said gate isapproximately 300 microns.
 11. The VCO of claim 1, wherein said sourceand said drain of said FET define a channel region therebetween withinsaid semiconductor layer, and wherein said gate of said FET forms aSchottky barrier with the respect to said channel region.
 12. The VCO ofclaim 11, wherein no pathway for DC return exists between said gate andsaid source or between said gate and said drain.
 13. A monolithicwideband voltage-controlled oscillator (VCO), comprising:an outputtransistor, said output transistor comprising first, second and thirdterminals.[., wherein said transistor amplifies across said second andthird terminals a signal provided thereto at said first terminal.].; afirst varactor, said varactor being direct current connected to saidfirst terminal of said transistor; first bias means, connected to saidfirst varactor, for providing a first selected bias voltage thereto; asecond varactor, direct current connected to said second terminal ofsaid transistor; second bias means, connected to said second varactorfor providing a second selected bias voltage thereto; and first andsecond RF ground connections, respectively connected to said first andsecond varactors respectively; said transistor and said varactors beingintegrated on a common monocrystalline substrate; whereby said thirdterminal of said transistor sustains oscillation.
 14. The VCO of claim13,wherein said first bias means provides said selected voltage to saidfirst varactor for generally matching the frequency of said oscillationat said third terminal of said transistor to a desired frequency; andwherein said second bias means provides said second selected biasvoltage to said second varactor for canceling the phase difference ofoscillations at said desired frequency between said second terminal ofsaid transistor and RF ground, to precisely match said oscillationfrequency to said desired frequency.
 15. The VCO of claim 14, whereinsaid respective RF ground connections comprises respective capacitorssharing a common layer of metallization.
 16. The VCO of claim 14,wherein no pathway for DC return exists between said first and secondnor between said first and third terminals of said transistor.
 17. TheVCO of claim 13, 14, 15 or 16, wherein said transistor and saidvaractors are all formed atop a common semi-insulating substrate. 18.The VCO of claim 17, wherein said transistor and said respectivevaractors are all formed within said semiconductor layer atop saidsubstrate.
 19. The VCO of claim 18, wherein each said varactorcomprises:an anode and a cathode formed on said semiconductor layer,said anode and cathode being coadjacent and spaced apart from eachother, said anode forming a Schottky barrier with said semiconductorlayer, the portion of said semiconductor layer beneath said anode beingsufficiently thin and sufficiently lightly doped that punch throughbetween said anode and said substrate occurs at a lower voltage thandoes breakdown between said anode and said cathode.
 20. The VCO of claim1, wherein said first terminal of said reactor is at least 2 micronswide.
 21. The VCO of claim 1, wherein said first terminal of saidreactor is at least 6 times as wide as said semiconducting layer beneathsaid first terminal is thick.
 22. The VCO of claim 1, wherein all of theperiphery of said first terminal of said first varactor is co-adjacentto respective corresponding portions of said second terminal saidvaractor.
 23. The VCO of claim 1, wherein said semiconducting layerbeneath said first terminal of said varactor is continuous with saidsemiconducting layer beneath said FET. .Iadd.
 24. A monolithic widebandmicrowave voltage-controlled oscillator, comprising:(a) asemi-insulating substrate; (b) a field effect transistor, said fieldeffect transistor with channel in a first doped semiconducting planarregion on said substrate; (c) a varactor, said varactor with anode andcathode on a second doped semiconducting planar region on saidsubstrate, said second region of substantially the same thickness anddoping concentration as said first region; and (d) interconnectionbetween said varactor and said field effect transistor with saidvaractor a controlled reactive feedback at a first terminal of saidtransistor. .Iaddend. .Iadd.25. The oscillator of claim 24, furthercomprising: (a) a second varactor on said substrate, said secondvaractor with anode and cathode on a third doped semiconducting planarregion on said substrate, said third region of substantially the samethickness and doping concentration as said first region; and (b)interconnection between said second varactor and said field effecttransistor with said second varactor a second controlled reactivefeedback at a second terminal of said transistor, said two varactorstogether controlling the frequency of oscillation. .Iaddend. .Iadd.26.The oscillator of claim 25, wherein: (a) said second and third regionseach have doping and thickness so that for each of said two varactorspunchthrough to said substrate occurs at a lower voltage than breakdownbetween anode and cathode. .Iaddend. .Iadd.27. The oscillator of claim24, wherein: (a) said first and second regions are mesas isolated fromeach other. .Iaddend.